1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit (IC) manufacturing, and more specifically, to a method of improving pattern recognition for critical dimension (CD) measurement in an optical microscope or a Scanning Electron Microscope (SEM).
2. Discussion of Related Art
During fabrication of an integrated circuit (IC), many parameters of the semiconductor devices must be monitored to maximize yield. In particular, it is desirable to measure critical dimension (CD) of certain features, especially on the critical layers such as shallow trench isolation, polysilicon gate, contact, and first metal.
The CD for a layer may be monitored in-line by sampling the product features on various die across a wafer. However, it is often advantageous to measure test structures that may be placed in the scribelines separating the die. CD measurements are usually performed after develop since rework is still possible at that point by stripping the photoresist. CD measurements are also done after etch to determine the etch bias.
CD measurements are often taken optically on a tool with conventional microscope optics or with laser-spot scanning. The resolution of an optical probe can be increased by about 30% if a confocal configuration is used. However, it is usually necessary to use a scanning electron microscope (SEM) to measure a CD smaller than about 200 nanometers. To avoid charging of the sample, the acceleration voltage should be kept below about 600 to 1000 volts or the vacuum should be kept low. Field emission guns are often used to produce good images.
A SEM may be used to measure the CD of a structure after develop or after etch. After loading a wafer into the SEM, a motorized stage moves the wafer to a specified location based on an external coordinate system. Then, pattern recognition of the captured image is performed to locate the desired structure in the vicinity. Finally, the CD of the structure is measured.
Although sophisticated algorithms are available for pattern recognition, various parameters in the recipe must still be empirically optimized to improve the robustness of the recipe. If the acceptance level is too relaxed, pattern recognition may mistakenly identify an incorrect feature. Then the corresponding CD measurement would not be meaningful, thus, degrading data integrity and compromising in-line process control. On the other hand, if the acceptance level is too stringent, the pattern recognition may fail, thus, mandating manual intervention by the user. At a minimum, the processing of the wafer is interrupted. Of even more concern is that the feedback from the SEM to the process tools is delayed, needlessly leading to production of more wafers that are out of specification and have to be scrapped.
Thus, what is needed is a structure for and a method of improving pattern recognition.